Move the UTMIPLL initialization code form clk-tegra<chip>.c files into
clk-pll.c. UTMIPLL was being configured and set in HW control right
after registration. However, when the clock init_table is processed and
child clks of PLLU are enabled, it will call in and enable PLLU as
well, and initiate SW enabling sequence even though PLLU is already in
HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status.
Doing the initialization once during pllu_enable means we configure it
properly into HW control.
A side effect of the commonization/localization of the UTMIPLL init
code, is that it corrects some errors that were present for earlier
generations. For instance, in clk-tegra124.c, it used to have: