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[PATCH 00/11] Clock improvement for video playback

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[PATCH 00/11] Clock improvement for video playback

Gabriel Fernandez-3
This serie allows to increase video resolutions and make audio
adjustment during a video playback.

Gabriel Fernandez (11):
  drivers: clk: st: Add fs660c32 synthesizer algorithm
  drivers: clk: st: Add clock propagation for audio clocks
  drivers: clk: st: Handle clkgenD2 clk synchronous mode
  ARM: DT: STiH407: Add compatibility string on clkgend0 for audio
    clocks
  ARM: DT: STiH410: Add compatibility string on clkgend0 for audio
    clocks
  ARM: DT: STiH418: Add compatibility string on clkgend0 for audio
    clocks
  ARM: DT: STiH407: Enable synchronous clock mode on clkgend2
  ARM: DT: STiH410: Enable synchronous clock mode on clkgend2
  ARM: DT: STiH418: Enable synchronous clock mode on clkgend2
  ARM: DT: STi: STiH407: clock configuration to address 720p and 1080p
  ARM: DT: STi: STiH410: clock configuration to address 720p and 1080p

 .../devicetree/bindings/clock/st/st,flexgen.txt    |   3 +
 arch/arm/boot/dts/stih407-clock.dtsi               |   4 +-
 arch/arm/boot/dts/stih407.dtsi                     |  16 ++-
 arch/arm/boot/dts/stih410-clock.dtsi               |   4 +-
 arch/arm/boot/dts/stih410.dtsi                     |  16 ++-
 arch/arm/boot/dts/stih418-clock.dtsi               |   4 +-
 drivers/clk/st/clk-flexgen.c                       |  61 +++++++-
 drivers/clk/st/clkgen-fsyn.c                       | 159 +++++++++++++++------
 8 files changed, 211 insertions(+), 56 deletions(-)

--
1.9.1

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[PATCH 04/11] ARM: DT: STiH407: Add compatibility string on clkgend0 for audio clocks

Gabriel Fernandez-3
This patch is used in the clock driver to apply a clock propagation
flag on the audio clocks of STiH407

Signed-off-by: Olivier Bideau <[hidden email]>
Signed-off-by: Gabriel Fernandez <[hidden email]>
---
 arch/arm/boot/dts/stih407-clock.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index ad45f5e..76c6984 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -216,7 +216,7 @@
 
  clk_s_d0_flexgen: clk-s-d0-flexgen {
  #clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,stih407-clkgend0", "st,flexgen";
 
  clocks = <&clk_s_d0_quadfs 0>,
  <&clk_s_d0_quadfs 1>,
--
1.9.1

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[PATCH 07/11] ARM: DT: STiH407: Enable synchronous clock mode on clkgend2

Gabriel Fernandez-3
In reply to this post by Gabriel Fernandez-3
This patch adds a compatibility string on clkgend2 to allow the clock
driver to handle the synchronous/asynchronous modes of STiH407

Signed-off-by: Olivier Bideau <[hidden email]>
Signed-off-by: Gabriel Fernandez <[hidden email]>
---
 arch/arm/boot/dts/stih407-clock.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index 76c6984..bdf3998 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -256,7 +256,7 @@
 
  clk_s_d2_flexgen: clk-s-d2-flexgen {
  #clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,stih407-clkgend2", "st,flexgen";
 
  clocks = <&clk_s_d2_quadfs 0>,
  <&clk_s_d2_quadfs 1>,
--
1.9.1

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[PATCH 10/11] ARM: DT: STi: STiH407: clock configuration to address 720p and 1080p

Gabriel Fernandez-3
In reply to this post by Gabriel Fernandez-3
It is necessary to properly configure these clocks in order
to address 720p and 1080p HDMI resolution.

Signed-off-by: Vincent Abriou <[hidden email]>
Signed-off-by: Gabriel Fernandez <[hidden email]>
---
 arch/arm/boot/dts/stih407.dtsi | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index d60f0d8..291ffac 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -16,7 +16,10 @@
  #size-cells = <1>;
 
  assigned-clocks = <&clk_s_d2_quadfs 0>,
-  <&clk_s_d2_quadfs 0>,
+  <&clk_s_d2_quadfs 1>,
+  <&clk_s_c0_pll1 0>,
+  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+  <&clk_s_c0_flexgen CLK_MAIN_DISP>,
   <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
   <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
   <&clk_s_d2_flexgen CLK_PIX_GDP1>,
@@ -26,14 +29,21 @@
 
  assigned-clock-parents = <0>,
  <0>,
+ <0>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_pll1 0>,
  <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
  <&clk_s_d2_quadfs 0>,
  <&clk_s_d2_quadfs 0>,
  <&clk_s_d2_quadfs 0>,
  <&clk_s_d2_quadfs 0>;
 
- assigned-clock-rates = <297000000>, <297000000>;
+ assigned-clock-rates = <297000000>,
+       <108000000>,
+       <0>,
+       <400000000>,
+       <400000000>;
 
  ranges;
 
--
1.9.1

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[PATCH 08/11] ARM: DT: STiH410: Enable synchronous clock mode on clkgend2

Gabriel Fernandez-3
In reply to this post by Gabriel Fernandez-3
This patch adds a compatibility string on clkgend2 to allow the clock
driver to handle the synchronous/asynchronous modes of STiH410

Signed-off-by: Olivier Bideau <[hidden email]>
Signed-off-by: Gabriel Fernandez <[hidden email]>
---
 arch/arm/boot/dts/stih410-clock.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
index c265e54..479e92d 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -268,7 +268,7 @@
 
  clk_s_d2_flexgen: clk-s-d2-flexgen {
  #clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,stih407-clkgend2", "st,flexgen";
 
  clocks = <&clk_s_d2_quadfs 0>,
  <&clk_s_d2_quadfs 1>,
--
1.9.1

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[PATCH 11/11] ARM: DT: STi: STiH410: clock configuration to address 720p and 1080p

Gabriel Fernandez-3
In reply to this post by Gabriel Fernandez-3
It is necessary to properly configure these clocks in order
to address 720p and 1080p HDMI resolution.

Signed-off-by: Vincent Abriou <[hidden email]>
Signed-off-by: Gabriel Fernandez <[hidden email]>
---
 arch/arm/boot/dts/stih410.dtsi | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 18ed1ad..7eec729 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -103,7 +103,10 @@
  #size-cells = <1>;
 
  assigned-clocks = <&clk_s_d2_quadfs 0>,
-  <&clk_s_d2_quadfs 0>,
+  <&clk_s_d2_quadfs 1>,
+  <&clk_s_c0_pll1 0>,
+  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+  <&clk_s_c0_flexgen CLK_MAIN_DISP>,
   <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
   <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
   <&clk_s_d2_flexgen CLK_PIX_GDP1>,
@@ -113,14 +116,21 @@
 
  assigned-clock-parents = <0>,
  <0>,
+ <0>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_pll1 0>,
  <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
  <&clk_s_d2_quadfs 0>,
  <&clk_s_d2_quadfs 0>,
  <&clk_s_d2_quadfs 0>,
  <&clk_s_d2_quadfs 0>;
 
- assigned-clock-rates = <297000000>, <297000000>;
+ assigned-clock-rates = <297000000>,
+       <108000000>,
+       <0>,
+       <400000000>,
+       <400000000>;
 
  ranges;
 
--
1.9.1

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[PATCH 09/11] ARM: DT: STiH418: Enable synchronous clock mode on clkgend2

Gabriel Fernandez-3
In reply to this post by Gabriel Fernandez-3
This patch adds a compatibility string on clkgend2 to allow the clock
driver to handle the synchronous/asynchronous modes of STiH418

Signed-off-by: Olivier Bideau <[hidden email]>
Signed-off-by: Gabriel Fernandez <[hidden email]>
---
 arch/arm/boot/dts/stih418-clock.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index 9740f41..4ae70a7 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -271,7 +271,7 @@
 
  clk_s_d2_flexgen: clk-s-d2-flexgen {
  #clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,stih407-clkgend2", "st,flexgen";
 
  clocks = <&clk_s_d2_quadfs 0>,
  <&clk_s_d2_quadfs 1>,
--
1.9.1

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[PATCH 06/11] ARM: DT: STiH418: Add compatibility string on clkgend0 for audio clocks

Gabriel Fernandez-3
In reply to this post by Gabriel Fernandez-3
This patch is used in the clock driver to apply a clock propagation
flag on the audio clocks of STiH418

Signed-off-by: Olivier Bideau <[hidden email]>
Signed-off-by: Gabriel Fernandez <[hidden email]>
---
 arch/arm/boot/dts/stih418-clock.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index ae6d997..9740f41 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -229,7 +229,7 @@
 
  clk_s_d0_flexgen: clk-s-d0-flexgen {
  #clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,stih407-clkgend0", "st,flexgen";
 
  clocks = <&clk_s_d0_quadfs 0>,
  <&clk_s_d0_quadfs 1>,
--
1.9.1

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[PATCH 02/11] drivers: clk: st: Add clock propagation for audio clocks

Gabriel Fernandez-3
In reply to this post by Gabriel Fernandez-3
This patch allows fine tuning of the quads FS for audio clocks
accuracy.

Signed-off-by: Olivier Bideau <[hidden email]>
Signed-off-by: Gabriel Fernandez <[hidden email]>
---
 .../devicetree/bindings/clock/st/st,flexgen.txt    |  1 +
 drivers/clk/st/clk-flexgen.c                       | 24 ++++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
index b7ee5c7..15b33c7 100644
--- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
@@ -60,6 +60,7 @@ This binding uses the common clock binding[2].
 Required properties:
 - compatible : shall be:
   "st,flexgen"
+  "st,stih407-clkgend0", "st,flexgen" (enable clock propagation on parent)
 
 - #clock-cells : from common clock binding; shall be set to 1 (multiple clock
   outputs).
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 627267c..3ff51ec 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -15,6 +15,10 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
+struct clkgen_data {
+ unsigned long flags;
+};
+
 struct flexgen {
  struct clk_hw hw;
 
@@ -259,6 +263,18 @@ static const char ** __init flexgen_get_parents(struct device_node *np,
  return parents;
 }
 
+static const struct clkgen_data clkgen_d0 = {
+ .flags = CLK_SET_RATE_PARENT,
+};
+
+static const struct of_device_id flexgen_of_match[] = {
+ {
+ .compatible = "st,stih407-clkgend0",
+ .data = &clkgen_d0,
+ },
+ {}
+};
+
 static void __init st_of_flexgen_setup(struct device_node *np)
 {
  struct device_node *pnode;
@@ -267,6 +283,8 @@ static void __init st_of_flexgen_setup(struct device_node *np)
  const char **parents;
  int num_parents, i;
  spinlock_t *rlock = NULL;
+ const struct of_device_id *match;
+ struct clkgen_data *data = NULL;
  unsigned long flex_flags = 0;
  int ret;
 
@@ -282,6 +300,12 @@ static void __init st_of_flexgen_setup(struct device_node *np)
  if (!parents)
  return;
 
+ match = of_match_node(flexgen_of_match, np);
+ if (match) {
+ data = (struct clkgen_data *)match->data;
+ flex_flags = data->flags;
+ }
+
  clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
  if (!clk_data)
  goto err;
--
1.9.1

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[PATCH 05/11] ARM: DT: STiH410: Add compatibility string on clkgend0 for audio clocks

Gabriel Fernandez-3
In reply to this post by Gabriel Fernandez-3
This patch is used in the clock driver to apply a clock propagation
flag on the audio clocks of STiH410

Signed-off-by: Olivier Bideau <[hidden email]>
Signed-off-by: Gabriel Fernandez <[hidden email]>
---
 arch/arm/boot/dts/stih410-clock.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
index d1f2aca..c265e54 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -226,7 +226,7 @@
 
  clk_s_d0_flexgen: clk-s-d0-flexgen {
  #clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,stih407-clkgend0", "st,flexgen";
 
  clocks = <&clk_s_d0_quadfs 0>,
  <&clk_s_d0_quadfs 1>,
--
1.9.1

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[PATCH 03/11] drivers: clk: st: Handle clkgenD2 clk synchronous mode

Gabriel Fernandez-3
In reply to this post by Gabriel Fernandez-3
This patch configures the semi-synchronous mode of the video clocks
of clkgenD2.

Signed-off-by: Olivier Bideau <[hidden email]>
Signed-off-by: Gabriel Fernandez <[hidden email]>
---
 .../devicetree/bindings/clock/st/st,flexgen.txt    |  2 ++
 drivers/clk/st/clk-flexgen.c                       | 37 ++++++++++++++++++++--
 2 files changed, 37 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
index 15b33c7..8b73831 100644
--- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
@@ -61,6 +61,8 @@ Required properties:
 - compatible : shall be:
   "st,flexgen"
   "st,stih407-clkgend0", "st,flexgen" (enable clock propagation on parent)
+  "st,stih407-clkgend2", "st,flexgen" (enable clock propagation on parent
+ and activate synchronous mode)
 
 - #clock-cells : from common clock binding; shall be set to 1 (multiple clock
   outputs).
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 3ff51ec..aad6f4b 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -17,6 +17,7 @@
 
 struct clkgen_data {
  unsigned long flags;
+ bool mode;
 };
 
 struct flexgen {
@@ -32,9 +33,14 @@ struct flexgen {
  struct clk_gate fgate;
  /* Final divisor */
  struct clk_divider fdiv;
+ /* Asynchronous mode control */
+ struct clk_gate sync;
+ /* hw control flags */
+ bool control_mode;
 };
 
 #define to_flexgen(_hw) container_of(_hw, struct flexgen, hw)
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
 
 static int flexgen_enable(struct clk_hw *hw)
 {
@@ -143,12 +149,21 @@ static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate,
  struct flexgen *flexgen = to_flexgen(hw);
  struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
  struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
+ struct clk_hw *sync_hw = &flexgen->sync.hw;
+ struct clk_gate *config = to_clk_gate(sync_hw);
  unsigned long div = 0;
  int ret = 0;
+ u32 reg;
 
  __clk_hw_set_clk(pdiv_hw, hw);
  __clk_hw_set_clk(fdiv_hw, hw);
 
+ if (flexgen->control_mode) {
+ reg = readl(config->reg);
+ reg &= ~BIT(config->bit_idx);
+ writel(reg, config->reg);
+ }
+
  div = clk_best_div(parent_rate, rate);
 
  /*
@@ -182,7 +197,7 @@ static const struct clk_ops flexgen_ops = {
 static struct clk *clk_register_flexgen(const char *name,
  const char **parent_names, u8 num_parents,
  void __iomem *reg, spinlock_t *lock, u32 idx,
- unsigned long flexgen_flags) {
+ unsigned long flexgen_flags, bool mode) {
  struct flexgen *fgxbar;
  struct clk *clk;
  struct clk_init_data init;
@@ -231,6 +246,13 @@ static struct clk *clk_register_flexgen(const char *name,
  fgxbar->fdiv.reg = fdiv_reg;
  fgxbar->fdiv.width = 6;
 
+ /* Final divider sync config */
+ fgxbar->sync.lock = lock;
+ fgxbar->sync.reg = fdiv_reg;
+ fgxbar->sync.bit_idx = 7;
+
+ fgxbar->control_mode = mode;
+
  fgxbar->hw.init = &init;
 
  clk = clk_register(NULL, &fgxbar->hw);
@@ -267,11 +289,20 @@ static const struct clkgen_data clkgen_d0 = {
  .flags = CLK_SET_RATE_PARENT,
 };
 
+static const struct clkgen_data clkgen_d2 = {
+ .flags = CLK_SET_RATE_PARENT,
+ .mode = 1,
+};
+
 static const struct of_device_id flexgen_of_match[] = {
  {
  .compatible = "st,stih407-clkgend0",
  .data = &clkgen_d0,
  },
+ {
+ .compatible = "st,stih407-clkgend2",
+ .data = &clkgen_d2,
+ },
  {}
 };
 
@@ -287,6 +318,7 @@ static void __init st_of_flexgen_setup(struct device_node *np)
  struct clkgen_data *data = NULL;
  unsigned long flex_flags = 0;
  int ret;
+ bool clk_mode = 0;
 
  pnode = of_get_parent(np);
  if (!pnode)
@@ -304,6 +336,7 @@ static void __init st_of_flexgen_setup(struct device_node *np)
  if (match) {
  data = (struct clkgen_data *)match->data;
  flex_flags = data->flags;
+ clk_mode = data->mode;
  }
 
  clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
@@ -345,7 +378,7 @@ static void __init st_of_flexgen_setup(struct device_node *np)
  continue;
 
  clk = clk_register_flexgen(clk_name, parents, num_parents,
-   reg, rlock, i, flex_flags);
+   reg, rlock, i, flex_flags, clk_mode);
 
  if (IS_ERR(clk))
  goto err;
--
1.9.1

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[PATCH 01/11] drivers: clk: st: Add fs660c32 synthesizer algorithm

Gabriel Fernandez-3
In reply to this post by Gabriel Fernandez-3
Use an algorithm instead of a table to compute clocks for fs660c32
synthesizer.
During a video playback we need to adjust audio & video frequencies.
A table can't cover all HDMI resolutions and audio adjustment.

Signed-off-by: Gabriel Fernandez <[hidden email]>
---
 drivers/clk/st/clkgen-fsyn.c | 159 +++++++++++++++++++++++++++++++------------
 1 file changed, 117 insertions(+), 42 deletions(-)

diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index dec4eaa..06e9537 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -81,40 +81,6 @@ static const struct stm_fs fs432c65_rtbl[] = {
  { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x0, .nsdiv = 1 }, /* 297     MHz */
 };
 
-static const struct stm_fs fs660c32_rtbl[] = {
- { .mdiv = 0x14, .pe = 0x376b, .sdiv = 0x4, .nsdiv = 1 }, /* 25.175  MHz */
- { .mdiv = 0x14, .pe = 0x30c3, .sdiv = 0x4, .nsdiv = 1 }, /* 25.200  MHz */
- { .mdiv = 0x10, .pe = 0x71c7, .sdiv = 0x4, .nsdiv = 1 }, /* 27.000  MHz */
- { .mdiv = 0x00, .pe = 0x47af, .sdiv = 0x3, .nsdiv = 0 }, /* 27.027  MHz */
- { .mdiv = 0x0e, .pe = 0x4e1a, .sdiv = 0x4, .nsdiv = 1 }, /* 28.320  MHz */
- { .mdiv = 0x0b, .pe = 0x534d, .sdiv = 0x4, .nsdiv = 1 }, /* 30.240  MHz */
- { .mdiv = 0x17, .pe = 0x6fbf, .sdiv = 0x2, .nsdiv = 0 }, /* 31.500  MHz */
- { .mdiv = 0x01, .pe = 0x0, .sdiv = 0x4, .nsdiv = 1 }, /* 40.000  MHz */
- { .mdiv = 0x15, .pe = 0x2aab, .sdiv = 0x3, .nsdiv = 1 }, /* 49.500  MHz */
- { .mdiv = 0x14, .pe = 0x6666, .sdiv = 0x3, .nsdiv = 1 }, /* 50.000  MHz */
- { .mdiv = 0x1d, .pe = 0x395f, .sdiv = 0x1, .nsdiv = 0 }, /* 57.284  MHz */
- { .mdiv = 0x08, .pe = 0x4ec5, .sdiv = 0x3, .nsdiv = 1 }, /* 65.000  MHz */
- { .mdiv = 0x05, .pe = 0x1770, .sdiv = 0x3, .nsdiv = 1 }, /* 71.000  MHz */
- { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x3, .nsdiv = 1 }, /* 74.176  MHz */
- { .mdiv = 0x0f, .pe = 0x3426, .sdiv = 0x1, .nsdiv = 0 }, /* 74.250  MHz */
- { .mdiv = 0x0e, .pe = 0x7777, .sdiv = 0x1, .nsdiv = 0 }, /* 75.000  MHz */
- { .mdiv = 0x01, .pe = 0x4053, .sdiv = 0x3, .nsdiv = 1 }, /* 78.800  MHz */
- { .mdiv = 0x09, .pe = 0x15b5, .sdiv = 0x1, .nsdiv = 0 }, /* 85.500  MHz */
- { .mdiv = 0x1b, .pe = 0x3f19, .sdiv = 0x2, .nsdiv = 1 }, /* 88.750  MHz */
- { .mdiv = 0x10, .pe = 0x71c7, .sdiv = 0x2, .nsdiv = 1 }, /* 108.000 MHz */
- { .mdiv = 0x00, .pe = 0x47af, .sdiv = 0x1, .nsdiv = 0 }, /* 108.108 MHz */
- { .mdiv = 0x0c, .pe = 0x3118, .sdiv = 0x2, .nsdiv = 1 }, /* 118.963 MHz */
- { .mdiv = 0x0c, .pe = 0x2f54, .sdiv = 0x2, .nsdiv = 1 }, /* 119.000 MHz */
- { .mdiv = 0x07, .pe = 0xe39, .sdiv = 0x2, .nsdiv = 1 }, /* 135.000 MHz */
- { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x2, .nsdiv = 1 }, /* 148.352 MHz */
- { .mdiv = 0x0f, .pe = 0x3426, .sdiv = 0x0, .nsdiv = 0 }, /* 148.500 MHz */
- { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x1, .nsdiv = 1 }, /* 296.704 MHz */
- { .mdiv = 0x03, .pe = 0x471c, .sdiv = 0x1, .nsdiv = 1 }, /* 297.000 MHz */
- { .mdiv = 0x00, .pe = 0x295f, .sdiv = 0x1, .nsdiv = 1 }, /* 326.700 MHz */
- { .mdiv = 0x1f, .pe = 0x3633, .sdiv = 0x0, .nsdiv = 1 }, /* 333.000 MHz */
- { .mdiv = 0x1c, .pe = 0x0, .sdiv = 0x0, .nsdiv = 1 }, /* 352.000 Mhz */
-};
-
 struct clkgen_quadfs_data {
  bool reset_present;
  bool bwfilter_present;
@@ -140,6 +106,7 @@ struct clkgen_quadfs_data {
  const struct clk_ops *pll_ops;
  const struct stm_fs *rtbl;
  u8 rtbl_cnt;
+ int  (*get_params)(unsigned long, unsigned long, struct stm_fs *);
  int  (*get_rate)(unsigned long , const struct stm_fs *,
  unsigned long *);
 };
@@ -156,6 +123,9 @@ static int clk_fs432c65_get_rate(unsigned long, const struct stm_fs *,
  unsigned long *);
 static int clk_fs660c32_dig_get_rate(unsigned long, const struct stm_fs *,
  unsigned long *);
+static int clk_fs660c32_dig_get_params(unsigned long input,
+ unsigned long output, struct stm_fs *fs);
+
 /*
  * Values for all of the standalone instances of this clock
  * generator found in STiH415 and STiH416 SYSCFG register banks. Note
@@ -266,8 +236,7 @@ static const struct clkgen_quadfs_data st_fs660c32_E_416 = {
  .lockstatus_present = true,
  .lock_status = CLKGEN_FIELD(0xAC, 0x1, 0),
  .pll_ops = &st_quadfs_pll_c32_ops,
- .rtbl = fs660c32_rtbl,
- .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
+ .get_params = clk_fs660c32_dig_get_params,
  .get_rate = clk_fs660c32_dig_get_rate,
 };
 
@@ -302,8 +271,7 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
  .lockstatus_present = true,
  .lock_status = CLKGEN_FIELD(0xEC, 0x1, 0),
  .pll_ops = &st_quadfs_pll_c32_ops,
- .rtbl = fs660c32_rtbl,
- .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
+ .get_params = clk_fs660c32_dig_get_params,
  .get_rate = clk_fs660c32_dig_get_rate,
 };
 
@@ -345,8 +313,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C = {
  .powerup_polarity = 1,
  .standby_polarity = 1,
  .pll_ops = &st_quadfs_pll_c32_ops,
- .rtbl = fs660c32_rtbl,
- .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
+ .get_params = clk_fs660c32_dig_get_params,
  .get_rate = clk_fs660c32_dig_get_rate,
 };
 
@@ -388,8 +355,7 @@ static const struct clkgen_quadfs_data st_fs660c32_D = {
  .powerup_polarity = 1,
  .standby_polarity = 1,
  .pll_ops = &st_quadfs_pll_c32_ops,
- .rtbl = fs660c32_rtbl,
- .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
+ .get_params = clk_fs660c32_dig_get_params,
  .get_rate = clk_fs660c32_dig_get_rate,};
 
 /**
@@ -893,12 +859,113 @@ static int quadfs_fsynt_get_hw_value_for_recalc(struct st_clk_quadfs_fsynth *fs,
  return 0;
 }
 
+static int clk_fs660c32_get_pe(int m, int si, unsigned long *deviation,
+ signed long input, unsigned long output, uint64_t *p,
+ struct stm_fs *fs)
+{
+ unsigned long new_freq, new_deviation;
+ struct stm_fs fs_tmp;
+ uint64_t val;
+
+ val = (uint64_t)output << si;
+
+ *p = (uint64_t)input * P20 - (32LL  + (uint64_t)m) * val * (P20 / 32LL);
+
+ *p = div64_u64(*p, val);
+
+ if (*p > 32767LL)
+ return 1;
+
+ fs_tmp.mdiv = (unsigned long) m;
+ fs_tmp.pe = (unsigned long)*p;
+ fs_tmp.sdiv = si;
+ fs_tmp.nsdiv = 1;
+
+ clk_fs660c32_dig_get_rate(input, &fs_tmp, &new_freq);
+
+ new_deviation = abs(output - new_freq);
+
+ if (new_deviation < *deviation) {
+ fs->mdiv = m;
+ fs->pe = (unsigned long)*p;
+ fs->sdiv = si;
+ fs->nsdiv = 1;
+ *deviation = new_deviation;
+ }
+ return 0;
+}
+
+static int clk_fs660c32_dig_get_params(unsigned long input,
+ unsigned long output, struct stm_fs *fs)
+{
+ int si; /* sdiv_reg (8 downto 0) */
+ int m; /* md value */
+ unsigned long new_freq, new_deviation;
+ /* initial condition to say: "infinite deviation" */
+ unsigned long deviation = ~0;
+ uint64_t p, p1, p2; /* pe value */
+ int r1, r2;
+
+ struct stm_fs fs_tmp;
+
+ for (si = 0; (si <= 8) && deviation; si++) {
+
+ /* Boundary test to avoid useless iteration */
+ r1 = clk_fs660c32_get_pe(0, si, &deviation,
+ input, output, &p1, fs);
+ r2 = clk_fs660c32_get_pe(31, si, &deviation,
+ input, output, &p2, fs);
+
+ /* No solution */
+ if (r1 && r2 && (p1 > p2))
+ continue;
+
+ /* Try to find best deviation */
+ for (m = 1; (m < 31) && deviation; m++)
+ clk_fs660c32_get_pe(m, si, &deviation,
+ input, output, &p, fs);
+
+ }
+
+ if (deviation == ~0) /* No solution found */
+ return -1;
+
+ /* pe fine tuning if deviation not 0: +/- 2 around computed pe value */
+ if (deviation) {
+ fs_tmp.mdiv = fs->mdiv;
+ fs_tmp.sdiv = fs->sdiv;
+ fs_tmp.nsdiv = fs->nsdiv;
+
+ if (fs->pe > 2)
+ p2 = fs->pe - 2;
+ else
+ p2 = 0;
+
+ for (; p2 < 32768ll && (p2 <= (fs->pe + 2)); p2++) {
+ fs_tmp.pe = (unsigned long)p2;
+
+ clk_fs660c32_dig_get_rate(input, &fs_tmp, &new_freq);
+
+ new_deviation = abs(output - new_freq);
+
+ /* Check if this is a better solution */
+ if (new_deviation < deviation) {
+ fs->pe = (unsigned long)p2;
+ deviation = new_deviation;
+
+ }
+ }
+ }
+ return 0;
+}
+
 static long quadfs_find_best_rate(struct clk_hw *hw, unsigned long drate,
  unsigned long prate, struct stm_fs *params)
 {
  struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
  int (*clk_fs_get_rate)(unsigned long ,
  const struct stm_fs *, unsigned long *);
+ int (*clk_fs_get_params)(unsigned long, unsigned long, struct stm_fs *);
  struct stm_fs prev_params;
  unsigned long prev_rate, rate = 0;
  unsigned long diff_rate, prev_diff_rate = ~0;
@@ -906,6 +973,14 @@ static long quadfs_find_best_rate(struct clk_hw *hw, unsigned long drate,
 
  clk_fs_get_rate = fs->data->get_rate;
 
+ if (fs->data->get_params) {
+ clk_fs_get_params = fs->data->get_params;
+
+ if (!clk_fs_get_params(prate, drate, params))
+ clk_fs_get_rate(prate, params, &rate);
+ return rate;
+ }
+
  for (index = 0; index < fs->data->rtbl_cnt; index++) {
  prev_rate = rate;
 
--
1.9.1

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Re: [PATCH 00/11] Clock improvement for video playback

Arnaud Pouliquen
In reply to this post by Gabriel Fernandez-3
Hello Gabriel,

Tested with success on stih407 family platforms

Reviewed-by: Arnaud Pouliquen <[hidden email]>
Tested-by: Arnaud Pouliquen <[hidden email]>

Regards
Arnaud

On 05/18/2016 10:41 AM, Gabriel Fernandez wrote:

> This serie allows to increase video resolutions and make audio
> adjustment during a video playback.
>
> Gabriel Fernandez (11):
>   drivers: clk: st: Add fs660c32 synthesizer algorithm
>   drivers: clk: st: Add clock propagation for audio clocks
>   drivers: clk: st: Handle clkgenD2 clk synchronous mode
>   ARM: DT: STiH407: Add compatibility string on clkgend0 for audio
>     clocks
>   ARM: DT: STiH410: Add compatibility string on clkgend0 for audio
>     clocks
>   ARM: DT: STiH418: Add compatibility string on clkgend0 for audio
>     clocks
>   ARM: DT: STiH407: Enable synchronous clock mode on clkgend2
>   ARM: DT: STiH410: Enable synchronous clock mode on clkgend2
>   ARM: DT: STiH418: Enable synchronous clock mode on clkgend2
>   ARM: DT: STi: STiH407: clock configuration to address 720p and 1080p
>   ARM: DT: STi: STiH410: clock configuration to address 720p and 1080p
>
>  .../devicetree/bindings/clock/st/st,flexgen.txt    |   3 +
>  arch/arm/boot/dts/stih407-clock.dtsi               |   4 +-
>  arch/arm/boot/dts/stih407.dtsi                     |  16 ++-
>  arch/arm/boot/dts/stih410-clock.dtsi               |   4 +-
>  arch/arm/boot/dts/stih410.dtsi                     |  16 ++-
>  arch/arm/boot/dts/stih418-clock.dtsi               |   4 +-
>  drivers/clk/st/clk-flexgen.c                       |  61 +++++++-
>  drivers/clk/st/clkgen-fsyn.c                       | 159 +++++++++++++++------
>  8 files changed, 211 insertions(+), 56 deletions(-)
>
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Re: [PATCH 02/11] drivers: clk: st: Add clock propagation for audio clocks

Rob Herring-3
In reply to this post by Gabriel Fernandez-3
On Wed, May 18, 2016 at 10:41:23AM +0200, Gabriel Fernandez wrote:

> This patch allows fine tuning of the quads FS for audio clocks
> accuracy.
>
> Signed-off-by: Olivier Bideau <[hidden email]>
> Signed-off-by: Gabriel Fernandez <[hidden email]>
> ---
>  .../devicetree/bindings/clock/st/st,flexgen.txt    |  1 +
>  drivers/clk/st/clk-flexgen.c                       | 24 ++++++++++++++++++++++
>  2 files changed, 25 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
> index b7ee5c7..15b33c7 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
> @@ -60,6 +60,7 @@ This binding uses the common clock binding[2].
>  Required properties:
>  - compatible : shall be:
>    "st,flexgen"
> +  "st,stih407-clkgend0", "st,flexgen" (enable clock propagation on parent)

What do "d0" and "d2" refer to?

This seems to indicate you have too much clock detail in the DT (with
individual clocks described) or not enough with genericish compatible
strings. What happens for the mext clock you need to adjust the flags
on? You should be able to make these adjustments without DT updates.
Perhaps you need a wider fixing of clock compatible strings.

Rob
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Re: [PATCH 02/11] drivers: clk: st: Add clock propagation for audio clocks

Gabriel Fernandez-3
On 25 May 2016 at 19:24, Rob Herring <[hidden email]> wrote:

>
> On Wed, May 18, 2016 at 10:41:23AM +0200, Gabriel Fernandez wrote:
> > This patch allows fine tuning of the quads FS for audio clocks
> > accuracy.
> >
> > Signed-off-by: Olivier Bideau <[hidden email]>
> > Signed-off-by: Gabriel Fernandez <[hidden email]>
> > ---
> >  .../devicetree/bindings/clock/st/st,flexgen.txt    |  1 +
> >  drivers/clk/st/clk-flexgen.c                       | 24 ++++++++++++++++++++++
> >  2 files changed, 25 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
> > index b7ee5c7..15b33c7 100644
> > --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
> > +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
> > @@ -60,6 +60,7 @@ This binding uses the common clock binding[2].
> >  Required properties:
> >  - compatible : shall be:
> >    "st,flexgen"
> > +  "st,stih407-clkgend0", "st,flexgen" (enable clock propagation on parent)
>
> What do "d0" and "d2" refer to?
>
> This seems to indicate you have too much clock detail in the DT (with
> individual clocks described) or not enough with genericish compatible
> strings. What happens for the mext clock you need to adjust the flags
> on? You should be able to make these adjustments without DT updates.
> Perhaps you need a wider fixing of clock compatible strings.
>
> Rob

Sorry i sent my response in html...

Hi Rob,

Thanks for reviewing.

Can i remove
"
st,stih407-clkgend0" & "
st,stih407-clkgend2" compatible strings and add proprieties instead ?
I only need to activate 2 features and then we can keep generic
compatible strings.

e.g.

clk_s_d2_flexgen: clk-s-d2-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen";
        ...
       st-sync-mode;
        st-update
-parent-rate;
};

for d0_flexgen i will enable only st-sync-mode;

Best Regards
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Re: [PATCH 02/11] drivers: clk: st: Add clock propagation for audio clocks

Rob Herring-3
On Thu, May 26, 2016 at 4:49 AM, Gabriel Fernandez
<[hidden email]> wrote:

> On 25 May 2016 at 19:24, Rob Herring <[hidden email]> wrote:
>>
>> On Wed, May 18, 2016 at 10:41:23AM +0200, Gabriel Fernandez wrote:
>> > This patch allows fine tuning of the quads FS for audio clocks
>> > accuracy.
>> >
>> > Signed-off-by: Olivier Bideau <[hidden email]>
>> > Signed-off-by: Gabriel Fernandez <[hidden email]>
>> > ---
>> >  .../devicetree/bindings/clock/st/st,flexgen.txt    |  1 +
>> >  drivers/clk/st/clk-flexgen.c                       | 24 ++++++++++++++++++++++
>> >  2 files changed, 25 insertions(+)
>> >
>> > diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>> > index b7ee5c7..15b33c7 100644
>> > --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>> > +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>> > @@ -60,6 +60,7 @@ This binding uses the common clock binding[2].
>> >  Required properties:
>> >  - compatible : shall be:
>> >    "st,flexgen"
>> > +  "st,stih407-clkgend0", "st,flexgen" (enable clock propagation on parent)
>>
>> What do "d0" and "d2" refer to?
>>
>> This seems to indicate you have too much clock detail in the DT (with
>> individual clocks described) or not enough with genericish compatible
>> strings. What happens for the mext clock you need to adjust the flags
>> on? You should be able to make these adjustments without DT updates.
>> Perhaps you need a wider fixing of clock compatible strings.
>>
>> Rob
>
> Sorry i sent my response in html...
>
> Hi Rob,
>
> Thanks for reviewing.
>
> Can i remove
> "
> st,stih407-clkgend0" & "
> st,stih407-clkgend2" compatible strings and add proprieties instead ?
> I only need to activate 2 features and then we can keep generic
> compatible strings.

That is no different and suffers the same point I raised. It requires
updating the DT for any clock configuration change or enhancement.

Rob
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Re: [STLinux Kernel] [PATCH 02/11] drivers: clk: st: Add clock propagation for audio clocks

Loic PALLARDY


On 05/26/2016 02:46 PM, Rob Herring wrote:

> On Thu, May 26, 2016 at 4:49 AM, Gabriel Fernandez
> <[hidden email]> wrote:
>> On 25 May 2016 at 19:24, Rob Herring <[hidden email]> wrote:
>>>
>>> On Wed, May 18, 2016 at 10:41:23AM +0200, Gabriel Fernandez wrote:
>>>> This patch allows fine tuning of the quads FS for audio clocks
>>>> accuracy.
>>>>
>>>> Signed-off-by: Olivier Bideau <[hidden email]>
>>>> Signed-off-by: Gabriel Fernandez <[hidden email]>
>>>> ---
>>>>   .../devicetree/bindings/clock/st/st,flexgen.txt    |  1 +
>>>>   drivers/clk/st/clk-flexgen.c                       | 24 ++++++++++++++++++++++
>>>>   2 files changed, 25 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>>>> index b7ee5c7..15b33c7 100644
>>>> --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>>>> +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>>>> @@ -60,6 +60,7 @@ This binding uses the common clock binding[2].
>>>>   Required properties:
>>>>   - compatible : shall be:
>>>>     "st,flexgen"
>>>> +  "st,stih407-clkgend0", "st,flexgen" (enable clock propagation on parent)
>>>
>>> What do "d0" and "d2" refer to?
>>>
>>> This seems to indicate you have too much clock detail in the DT (with
>>> individual clocks described) or not enough with genericish compatible
>>> strings. What happens for the mext clock you need to adjust the flags
>>> on? You should be able to make these adjustments without DT updates.
>>> Perhaps you need a wider fixing of clock compatible strings.
>>>
>>> Rob
>>
>> Sorry i sent my response in html...
>>
>> Hi Rob,
>>
>> Thanks for reviewing.
>>
>> Can i remove
>> "
>> st,stih407-clkgend0" & "
>> st,stih407-clkgend2" compatible strings and add proprieties instead ?
>> I only need to activate 2 features and then we can keep generic
>> compatible strings.
>
Hi Rob,
> That is no different and suffers the same point I raised. It requires
> updating the DT for any clock configuration change or enhancement.
>
Agree with you, DT update is needed as soon as a clock configuration
should be changed. This is due to STiH clock driver design based on DT
description of SoC clock tree.

This clock driver was accepted 2 years ago. At the time being there was
discussion about clock tree description location: driver or DT.
Bad choice was done for this driver...

If we decide to redesign STiH clock driver using in-driver clock tree
description, this will modify STiH clock DT nodes description and so
break DT backward compatibility.

What's from your pov the best option?

Regards,
Loic

> Rob
>
> _______________________________________________
> Kernel mailing list
> [hidden email]
> http://www.stlinux.com/mailman/listinfo/kernel
>
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Re: [STLinux Kernel] [PATCH 02/11] drivers: clk: st: Add clock propagation for audio clocks

Rob Herring-3
On Thu, May 26, 2016 at 8:05 AM, loic pallardy <[hidden email]> wrote:

>
>
> On 05/26/2016 02:46 PM, Rob Herring wrote:
>>
>> On Thu, May 26, 2016 at 4:49 AM, Gabriel Fernandez
>> <[hidden email]> wrote:
>>>
>>> On 25 May 2016 at 19:24, Rob Herring <[hidden email]> wrote:
>>>>
>>>>
>>>> On Wed, May 18, 2016 at 10:41:23AM +0200, Gabriel Fernandez wrote:
>>>>>
>>>>> This patch allows fine tuning of the quads FS for audio clocks
>>>>> accuracy.
>>>>>
>>>>> Signed-off-by: Olivier Bideau <[hidden email]>
>>>>> Signed-off-by: Gabriel Fernandez <[hidden email]>
>>>>> ---
>>>>>   .../devicetree/bindings/clock/st/st,flexgen.txt    |  1 +
>>>>>   drivers/clk/st/clk-flexgen.c                       | 24
>>>>> ++++++++++++++++++++++
>>>>>   2 files changed, 25 insertions(+)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>>>>> b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>>>>> index b7ee5c7..15b33c7 100644
>>>>> --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>>>>> +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>>>>> @@ -60,6 +60,7 @@ This binding uses the common clock binding[2].
>>>>>   Required properties:
>>>>>   - compatible : shall be:
>>>>>     "st,flexgen"
>>>>> +  "st,stih407-clkgend0", "st,flexgen" (enable clock propagation on
>>>>> parent)
>>>>
>>>>
>>>> What do "d0" and "d2" refer to?
>>>>
>>>> This seems to indicate you have too much clock detail in the DT (with
>>>> individual clocks described) or not enough with genericish compatible
>>>> strings. What happens for the mext clock you need to adjust the flags
>>>> on? You should be able to make these adjustments without DT updates.
>>>> Perhaps you need a wider fixing of clock compatible strings.
>>>>
>>>> Rob
>>>
>>>
>>> Sorry i sent my response in html...
>>>
>>> Hi Rob,
>>>
>>> Thanks for reviewing.
>>>
>>> Can i remove
>>> "
>>> st,stih407-clkgend0" & "
>>> st,stih407-clkgend2" compatible strings and add proprieties instead ?
>>> I only need to activate 2 features and then we can keep generic
>>> compatible strings.
>>
>>
> Hi Rob,
>>
>> That is no different and suffers the same point I raised. It requires
>> updating the DT for any clock configuration change or enhancement.
>>
> Agree with you, DT update is needed as soon as a clock configuration should
> be changed. This is due to STiH clock driver design based on DT description
> of SoC clock tree.
>
> This clock driver was accepted 2 years ago. At the time being there was
> discussion about clock tree description location: driver or DT.
> Bad choice was done for this driver...
>
> If we decide to redesign STiH clock driver using in-driver clock tree
> description, this will modify STiH clock DT nodes description and so break
> DT backward compatibility.
>
> What's from your pov the best option?

You can break it once or every time you need a clock change. I'd go
with the former. Maybe more specific compatible strings throughout
alone would be enough rather than a flag day changing the binding.

Rob
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